Dswitch: Write-aware Dynamic Inclusion Property Switching for Emerging Asymmetric Memory Technologies

Emerging non-volatile memory (NVM) technologies, such as spin-transfer torque RAM (STT-RAM), are attractive options for replacing or augmenting SRAM in implementing last-level caches (LLCs). However, the asymmetric read/write energy and latency associated with NVM introduces new challenges in designing caches where, in contrast to SRAM, dynamic energy from write operations can be responsible for a larger fraction of total cache energy than leakage. These properties lead to the fact that no single traditional inclusion policy being dominant in terms of LLC energy consumption for asymmetric LLCs. We propose a novel selective inclusion policy, Dswitch, to reduce energy consumption in LLCs with asymmetric read/write properties. Dswitch dynamically selects the better inclusion property between non-inclusive and exclusive modes at individual program phases, depending on the cache capacity requirement and the write traffic to the LLC. Results show that Dswitch outperforms other variants of selective inclusion policies and provides up to 48% (average 10%) and 34% (average 2%) energy savings over non-inclusive and exclusive STT-RAM LLCs, respectively. In the system with SRAM/STTRAM hybrid LLCs, Dswitch can also help to save energy with minimal hardware overheads.